EDMS105N

The EDMS105N general purposes microcontroller is based on the ARM Cortex-M0 32-bit architecture and presents an extremely low power consumption, both in active and standby mode.

The EDMS105N general purposes microcontroller is based on the ARM Cortex-M0 32-bit architecture and presents an extremely low power consumption, both in active and standby mode. This makes it perfectly suited for sensing applications that operate for extended period of time in standby mode while still requiring processing capabilities. It is packed with multiple peripherals for communication, timing, sensing or security purposes along with memories, oscillators, integrated power regulators and an intelligent multi-mode power management unit. This extremely low-power, highly-integrated microcontroller will turn any sensing edge devices into true install and forget systems.

Performances:
– 32-bit ARM Cortex-M0, 24 MHz operating frequency
– Supply voltage: 1.8-3.3 V
– Active current (CoreMark): 18 µA/MHz
– DeepSleep current (RTC + 8 kB SRAM retention): 340 nA

Power Management:
– Highly efficient built-in inductive buck converters
– LDOs for reduced BOM or improved supply stability
– Multiple, easy to use operating modes based on ARM Active, Sleep and Deepsleep modes for different levels of
power and clock gating
– 1 MHz LP mode for instantaneous power reduction

Memories:
– 256 kB of non-volatile single-cycle flash memory with instruction cache
– 32 kB of SRAM memory
– SRAM retention available per 8 kB bank in Deepsleep

System:
– 8-channel DMA controller for coreless memory transfers
– Inter-peripheral signalling for coreless peripheral communication
– Single Wire Debug interface
– Clock gating and scaling available by peripheral

Oscillators:
– Internal RC oscillators (32.768 kHz, 1 MHz and 24 MHz)
– Crystal drivers (32.768 kHz and up to 32 MHz)

Communication:
– One UART with 8-byte FIFO
– One debug UART (no FIFO, TX only)
– Two master/slave SPI with multi-master support, up to 4
chip select, 8-byte FIFO
– Two master/slave I2C with multi-master support, 7- and
10-bit addressing modes, up to FM+ (1 Mbit/s)
– Two master/slave/controller I2S, 8 to 32 bits word size,
16-byte FIFO
– Up to 48 GPIOs

Technical Details

Additional information

Supplier

Package

QFN48

Size

6mm x 6mm

Send a Product Inquiry

By submitting the request, your data will be processed to get in contact with you and answer your questions. For more information about the processing of your data, please take a look at our Privacy Policy.